DocID026506 Rev 1

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AN4539

HRTIM operating principles basics

32

The Timer A generates two phase-shifted 33.333kHz PWMs with 25% duty cycle on TA1

and TA2, with the following conditions:

•

TA1: Set on TA Period, reset on TA CMP1

•

TA2: Set on TA CMP2, reset on TA CMP3

The timer A period is below the minimum frequency available at the highest resolution, as

shown in Table 2:

In this case, the frequency prescaler must be set to 4 and the period calculated as following:

PER = fHRCK / fPWM. Here, a frequency of 33.333 kHz is obtained by setting PER register

to (144MHz * 8) / 33.333kHz) = 34560d (0x8700).

Even though the duty cycle is not updated in this example, and to be close to a practical use

case, the register preload mechanism is enabled with the PREEN bit. The REP (repetition)

event triggers the transfer of the preload registers on each and every period beginning.

Note:

A delay can be noticed at the PWM start-up, between TA1/TA2 and TD1/TD2 waveform.

This delay is normal and due to the fact that the 1st update event (causing compare

registers to take their programmed value) occurs only after the 1st counting period is

elapsed. Should the waveforms be started without this delay, it is possible to force a register

update by software (using TASWU and TDSWU bits) to have all active compare registers

contents updated at once.

CKPSC[2:0]

Prescaling

ratio

equivalent frequency

Resolution

Minimum

PWM frequency

000

1

144x32 MHz = 4.608 GHz

217 ps

70.3 kHz

001

2

144x16 MHz = 2.304 GHz

434 ps

35.1 kHz

010

4

144x8 MHz = 1.152 GHz

868 ps

17.6 kHz

011

8

144x4 MHz = 576 MHz

1.73 ns

8.8 kHz

100

16

144x2 MHz = 288 MHz

3.47 ns

4.4 kHz

101

32

144MHz

6.95 ns

2.2 kHz

110

64

144/2 MHz = 72 MHz

13.88 ns

1.1 kHz

111

128

144/4 MHz = 36 MHz

27.7 ns

550 Hz