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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AN4472 датащи(PDF) 13 Page - STMicroelectronics |
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AN4472 датащи(HTML) 13 Page - STMicroelectronics |
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13 / 44 page  DocID026198 Rev 1 13/44 AN4472 Hardware layout and configuration 44 Figure 7. Acquisition by Program 0 with SEL=0, where C1, C2, C3 and C4 are XDCR_1, XDCR_2, XDCR_3 and XDCR_4 respectively 3.4.3 Pattern Program 1 (SEL = 1, 5-level output option) The second pattern stored in the SPI Flash is described in Table 10, where the output pulses are delayed by 10 ns each. The state sequence is given in Table 11. The test conditions applied to generate the waveforms in Figure 8 and Figure 9 are: – HVP0 = + 80 V – HVP1 = + 40 V – HVM0 = - 80 V – HVM1 = - 40 V – Load: 300 pF // 100 Ω Table 10. Program “1” mode Frequency [MHz] Number of pulses Initial pulse PRF H-Bridge XDCR_1 PW 5 10 positive 150 µs TX0, TX1 XDCR_2 PW 5 10 positive 150 µs TX0, TX1 XDCR_3 PW 5 10 positive 150 µs TX1, TX1 XDCR_4 PW 5 10 positive 150 µs TX1, TX1 |
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