LTC3203/LTC3203-1

LTC3203B/LTC3203B-1

14

32031fa

APPLICATIO S I FOR ATIO

LTC3203/LTC3203B COMPONENTS NOT USED

IN LTC3203-1 OR LTC3203B-1

GROUND PLANE

3206 F07

1

2

3

4

5

10

9

8

7

6

C2

C1

11

Figure 6. Recommended Layouts

Thermal Management

For higher input voltages and maximum output current,

there can be substantial power dissipation in the LTC3203/

LTC3203-1/LTC3203B/LTC3203B-1. If the junction tem-

perature increases above approximately 150

°C, the ther-

mal shutdown circuitry will automatically deactivate the

output. To reduce the maximum junction temperature, a

good thermal connection to the PC board is recommended.

Connecting GND (Pin 9) and the exposed pad (Pin 11) of

the DFN package to a ground plane under the device on two

layers of the PC board can reduce the thermal resistance

of the package and PC board considerably.

Layout Considerations

Due to the high switching frequency and high transient

currents produced by the LTC3203/LTC3203-1/

LTC3203B/LTC3203B-1, careful board layout is neces-

sary for optimum performance. A true ground plane and

short connections to all the external capacitors will

improve performance and ensure proper regulation

under all conditions.

very high edge rate waveforms. The large dV/dt on these

pins can couple energy capacitively to adjacent printed

circuit board runs. Magnetic fields can also be generated

if the flying capacitors are not close to the part (i.e. the loop

area is large). To decouple capacitive energy transfer, a

Faraday shield may be used. This is a grounded PC trace

between the sensitive node and the LTC3203/LTC3203-1/

LTC3203B/LTC3203B-1 pins. For a high quality AC ground

it should be returned to a solid ground plane that extends

all the way to the LTC3203/LTC3203-1/LTC3203B/

LTC3203B-1. To prevent degraded performance, the FB

trace should be kept away or be shielded from the flying

capacitor traces.