13

µPD72107

When bus master (1)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

CLK cycle time

121

1000

ns

CLK low-level time

50

ns

CLK high-level time

50

ns

CLK rise time

1.5 – 3.0 V

10

ns

CLK fall time

3.0 – 1.5 V

10

ns

Load condition

Caution If the load capacitance exceeds 50 pF due to the configuration of the circuit, keep the load

capacitance of this device to within 50 pF by inserting a buffer or by some other means.

Remark DUT: device under test

AC test input/output waveform (except clock)

System clock

DUT

2.2 V

0.8 V

2.2 V

0.8 V

2.4 V

0.4 V

Test points

1.5 V

3.0 V

CLK