Sigma-delta (SD) vs. successive approximation register (SAR) analog-to-digital converters

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Doc ID 023945 Rev 1

Table 4.

SDADC vs. SAR ADC feature comparison

Feature

SDADC

SAR ADC

Max sampling rate

1.

The sampling rate is 50 ksps when selecting a single channel and 16.6 ksps when multiplexing between

different channels.

1 Msps

Resolution

16 bits

12 bits

Input mode

Single-ended differential

Single-ended

Embedded gains

0.5x to 32x

No

Number of channels

5 differential input pairs or 9

single-ended inputs

16 single-ended inputs

Number of instances

3 with synchro capability

1

Automatic Offset calibration

Yes

Yes

Analog watchdog

No

Yes

Trigger sources for regular

conversion

–Software

– Start of conversion of another

SDADC

– Software

– Embedded timers

– External events

Trigger sources for injected

conversion

–Software

– Embedded timers

– External events

– Start of conversion of another

SDADC

– Software

– Embedded timers

– External events

Input range

Reference voltage

1.22 V

1.8 V

VDDSD

VREFSD+

2.

For SDADC, the input impedance depends on the selected gain and the selected operating frequency

(1.5 MHz or 6 MHz).

For SAR ADC, the input impedance depends on used sampling frequency (0.05 - 1 MHz) and sampling

capacitor (8pF).

47 K

 to 540 K

125 K

 to 2500 K