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AN4195 датащи(PDF) 5 Page - STMicroelectronics

номер детали AN4195
подробное описание детали  STM32F30x ADC modes and application
PDF  24 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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AN4195 датащи(HTML) 5 Page - STMicroelectronics

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Comparison between ADC F1 family and F3 family
Differential mode
To configure the ADC channels to differential mode, first disable the ADC (ADCAL=0,
JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Select
differential input mode by programming DIFSEL[15:1] in the ADC_DIFSEL register.
Note:
If ADC analog input Channel-i is configured in differential, DIFSEL[i] should be set to ’1’.
The analog voltage to be converted for channel “i” is the difference between the external
voltage ADC_INi (positive input) and ADC_INi+1 (negative input).
1.1.3
Auto-Delay controller
The Auto delayed-conversions are useful to simplify the software as well as to optimize
performance of applications clocked at low frequency where there would be a risk to
encounter an ADC overrun. When the autodelay feature is enabled (AUTDLY=1), a new
conversion can start only if all the previous data of the same group has been treated:
For the regular conversion group, once the ADC_DR register is read or the EOC flag is
cleared.
For the injected conversion group, once the JEOCS is cleared.
1.2
Difference between STM32ADC F1 and F3 family
The STM32F1 family and STM32F3 family embed the same type of the ADC, the
successive approximation register (SAR) ADC.
But there are some difference in term of features, the following table present a comparison
between the two ADCs.
Table 2. ADC F1 and ADC F3 families comparison
Feature
ADC F1 family
ADC F3 family
Max sampling rate
1 Msps
5 Msps
Resolution
12 bits
6/8/10/12 bits
Input range
[VREF-, VREF+][VREF-, VREF+]
ADC Clock
AHB clock
AHB clock / PLL clock
Input mode
Single-ended
Single-ended and differential
Number of channels
16 single-ended inputs
15 single ended/ differential inputs
+ 3 internal single-ended channels
Analog watchdog
1 AWDG
3 AWGD
Trigger sources for regular
conversion
– Software
– Embedded timers
– External events
– Software
– Embedded timers
– External events
Trigger sources for injected
conversion
– Software
– Embedded timers
– External events
– Software
– Embedded timers
– External events
Number of instances
1 or 2
4
Dual mode
Yes
Yes



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