UM0843 datasheet(22/48 Pages) STMICROELECTRONICS

22 / 48 page

Block descriptions

UM0843

22/48

Doc ID16543 Rev 2

6.14

CPLD

The board includes a XILINX CPLD (U38) that implement E1 PHY initial configuration,

HDLC-RS485 on-board clocks generation, HDLC-TDM on-board clocks/syncs generation

and timing matching for CPU EMI bus to access E1 PHY internal registers.

J8 is the connector for CPLD JTAG emulator to download programming file.

6.15

LEDs

There are 2 general purpose LEDs (D33,D34) available on the left side of the board. All

LEDs are driven on when the related CPLD IO pin is driven high.

GPIO59 (D33), GPIO58 (D34)

6.16

Reset button

A manual reset button (SW1) is available on the board's right side.

6.17

Debug Interface

A debug interface is provided:

The JTAG interface provides "static" debug capability. This means that it is possible to set a

breakpoint and, when the system stops, to verify the contents of the memory and/or

registers and modify them if needed.

6.18

Power supply

This block, receiving 5V from an external AC/DC regulator will provide all the

Voltage needed that are:

●

1.2V (Switching regulator PM6641) to supply the internal logic of SPEAr310

●

1.8V (Switching regulator PM6641) for the DDR2memory

●

2.5V (LDO 1117A regulator) for the analog portion of SPEAr310

●

3.3V (Switching regulator PM6641) to supply the other interfaces

The board is protected against over voltage by U61 (STBP120DVDK6F).

A power monitor is also present to provide the general reset for the board.

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