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RM0312 датащи(PDF) 274 Page - STMicroelectronics |
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RM0312 датащи(HTML) 274 Page - STMicroelectronics |
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274 / 275 page ![]() Revision history RM0312 274/275 DocID022352 Rev 3 23 Revision history Table 57. Document revision history Date Revision Changes 28-Oct-2011 1 Initial release 20-Mar-2012 2 Changed title to “STM8TL5xxx microcontroller family” to cover STM8T52x and STM8TL53x devices Added PCODE description to Section 4.4: Memory organization on page 26. 08-Oct-2013 3 Replaced CLK_CCOR reset value to 0x10. Updated CCOSLP0 bit reset value to 1 in Table 16: CLK register map and reset values. Added Chapter 11: System configuration controller (SYSCFG). Updated bit3 of SPI_CR1 register in Section 20.5: SPI register map and reset values. Updated Internal signal name related to the timer input filtered edge detector and the description of TRGO in Table 33: Glossary of internal timer signals. Updated the Figure 19: TIMx general block diagram and Figure 30: Clock/trigger controller block diagram. Added sub section SCL master clock generation in section Section 19.4.2: I2C master mode. Updated FREQ bit description in Section 19.7.3: Frequency register (I2C_FREQR). Updated TRISE bit description in Section 19.7.14: TRISE register (I2C_TRISER). Updated the notes of CCR bits in both Section 19.7.12: Clock control register low (I2C_CCRL) and Section 19.7.13: Clock control register high (I2C_CCRH). Updated range of FREQ bits in Section 19.7.3: Frequency register (I2C_FREQR). Updated the disclaimer. |
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