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RM0312 датащи(PDF) 269 Page - STMicroelectronics |
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RM0312 датащи(HTML) 269 Page - STMicroelectronics |
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269 / 275 page ![]() DocID022352 Rev 3 269/275 RM0312 ProxSense™ (PXS) 273 22.9.23 Receiver Status Register for Rx[9:8] (PXS_RXSRH) Address offset: 0x1E Reset value: 0x00 22.9.24 Receiver Status Register for Rx[7:0] (PXS_RXSRL) Address offset: 0x1F Reset value: 0x00 7654321 0 Reserved VALID9 VALID8 rr 7654321 0 VALID7 VALID6 VALID5 VALID4 VALID3 VALID2 VALID1 VALID0 rrrrrrr r Bits 15:10 Reserved Bits 9:0 VALIDn: Valid bit for conversion data for receiver channel n is valid 0: RXnCNTR is ‘0’ and not valid 1: RXnCNTR is valid As soon as the voltage on a Cs capacitor has reached the threshold voltage (VTHR), its data register is updated and the corresponding VALIDn bit is set. PXS_RXSR is cleared at the start of each conversion (when START transitions from ‘0’ to ‘1’). PXS_RXSR is also cleared when PXSEN = 0. VALIDn remains cleared when the channel is disabled (RXENn = 0), or when it is in Projected transmitting mode (RXCR1/2/3_n is ‘011’). It also remains cleared if the corresponding channel’s data reaches 65535 (0xFFFF) if MAXENn is cleared or exceeds MAX[15:0] and MAXENn is ‘1’. |
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