RM0312 datasheet(216/275 Pages) STMICROELECTRONICS

216 / 275 page

Serial peripheral interface (SPI)

RM0312

216/275

DocID022352 Rev 3

In master unidirectional receive-only mode (MSTR = 1, BDM = 0, RXONLY = 1)

or bidirectional receive mode (MSTR = 1, BDM = 1, BDOE = 0):

This case must be managed in a particular way to ensure that the SPI does not initiate a

new transfer:

Wait for the second to last occurrence of RXNE = 1 (n-1)

Then wait for one SPI clock cycle (using a software loop) before disabling the SPI

(SPE = 0)

Then wait for the last RXNE=1 before entering Halt mode (or disabling the peripheral

clock).

Note:

In master bidirectional receive mode (MSTR=1 and BDM=1 and BDOE=0), the BSY flag is

kept low during a transfer.

In slave receive-only mode (MSTR = 0, BDM = 0, RXONLY = 1) or bidirectional

receive mode (MSTR = 0, BDM = 1, BDOE = 0):

You can disable the SPI (write SPE = 1) whenever you want: the current transfer will

complete before being effectively disabled.

Then, if you want to enter Halt mode, you must first wait until BSY = 0 before entering

Halt mode (or disabling the peripheral clock).

20.3.8

Error flags

Master mode fault (MODF)

Master mode fault occurs when the master device has its NSS pin pulled low (in NSS

hardware mode) or SSI bit low (in NSS software mode), this automatically sets the MODF

bit. Master mode fault affects the SPI peripheral in the following ways:

•

The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.

•

The SPE bit is reset. This blocks all output from the device and disables the SPI

interface.

•

The MSTR bit is reset, thus forcing the device into slave mode.

Use the following software sequence to clear the MODF bit:

Make a read or write access to the SPI_SR register while the MODF bit is set.

Then write to the SPI_CR1 register.

To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin

must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can

be restored to their original state after this clearing sequence.

As a security, hardware does not allow you to set the SPE and MSTR bits while the MODF

bit is set.

In a slave device the MODF bit cannot be set. However, in a multi-master configuration, the

device can be in slave mode with this MODF bit set. In this case, the MODF bit indicates

that there might have been a multimaster conflict for system control. You can use an

interrupt routine to recover cleanly from this state by performing a reset or returning to a

default state.

RM0312 датащи(PDF) 216 Page - STMicroelectronics

RM0312 датащи(HTML) 216 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL