RM0312 datasheet(211/275 Pages) STMICROELECTRONICS

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RM0312

Serial peripheral interface (SPI)

223

Transmit-only procedure (BDM = 0 RXONLY = 0)

In this mode, the procedure can be reduced as described below and the BSY bit can be

used to wait until the effective completion of the transmission (see Figure 75 and Figure 76):

Enable the SPI by setting the SPE bit

Write the first data to send in the SPI_DR register (this clears the TXE bit).

Wait until TXE = 1 and write the next data to be transmitted. Repeat this step for each

data to be transmitted.

After writing the last data in the SPI_DR register, wait until TXE = 1 and then wait until

BSY=0 which indicates that the transmission of the last data is complete.

This procedure can be also implemented using dedicated interrupt subroutines launched at

each rising edge of TXE flag.

Note:

In master mode, during discontinuous communications, there is a 2 CPU clock period delay

between the write operation to SPI_DR and the BSY bit setting. As a consequence, in

transmit-only mode, it is mandatory to wait first until TXE is set and then until BSY is reset

after having written the last data.

After transmitting two data in transmit-only mode, the OVR flag is set in the SPI_SR register

since the received data are never read.

Figure 77. TXE/BSY in master transmit-only mode

(BDM = 0 and RXONLY = 0). Case of continuous transfers

0xF1

Tx Buffer

TXE flag

0xF2

BSY flag

0xF3

software

writes 0xF1 in

SPI_DR

software waits until

TXE=1 and writes

0xF2 in SPI_DR

set by hw

cleared by sw

set by hw

cleared by sw

set by hw

SCK

reset by hw

Example in master mode with CPOL=1, CPHA=1

(write SPI_DR)

MISO/MOSI (out)

DATA 1 = 0xF1

DATA 2 = 0xF2

DATA 3 = 0xF3

software waits until

TXE=1 and writes 0xF3

in SPI_DR

software waits until BSY=0

software waits until

TXE=1

b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

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