RM0312 datasheet(151/275 Pages) STMICROELECTRONICS

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RM0312

16-bit general purpose timer (TIM2/TIM3)

170

17.7.9

Capture/compare mode register 1 (TIMx_CCMR1)

The channel can be used in input (capture mode) or in output (compare mode). The

direction of the channel is defined by configuring the CC1S bits. All the other bits of this

describes its function when the channel is configured in output, ICxx describes its function

when the channel is configured in input. So be aware that the same bit can have a different

meaning for the input stage and for the output stage.

Address offset: 0x08

Reset value: 0x00

Channel configured in output

654

3210

Reserved

OC1M[2:0]

OC1PE

OC1FE

CC1S[1:0]

Bit 7 Reserved

Bits 6:4 OC1M: Output compare 1 mode

These bits defines the behavior of the output reference signal OC1REF from which OC1 is derived.

OC1REF is active high whereas OC1 active level depends on the CC1P bit.

000 : Frozen - The comparison between the output compare register TIMx_CCR1 and the counter

TIMx_CNT has no effect on the outputs.

001 : Set channel 1 to active level on match. OC1REF signal is forced high when the counter

TIMx_CNT matchs the capture/compare register 1 (TIMx_CCR1).

010 : Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter

TIMx_CNT matchs the capture/compare register 1 (TIMx_CCR1).

011 : Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.

100 : Force inactive level - OC1REF is forced low.

101 : Force active level - OC1REF is forced high.

110 : PWM mode 1 - In up-counting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else

inactive. In down-counting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1

else active (OC1REF=’1’).

111 : PWM mode 2 - In up-counting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else

active.

Note: In PWM mode 1 or 2, the OCiREF level changes only when the result of the comparison

changes or when the output compare mode switches from “frozen” mode to “PWM” mode.

Refer to Section 17.5.7 on page 134 for more details.

Bit 3 OC1PE: Output compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value

is taken in account immediately.

1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.

TIMx_CCR1 preload value is loaded in the shadow register at each update event.

Note: For correct operation, preload registers must be enabled when the timer is in PWM mode. This

is not mandatory in one pulse mode (OPM bit set in TIMx_CR1 register).

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