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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UM0225 датащи(PDF) 21 Page - STMicroelectronics |
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UM0225 датащи(HTML) 21 Page - STMicroelectronics |
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21 / 57 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UM0225 3 Designing with CAPS 20/56 Selecting the Main Oscillator input clock - 4 to 25 MHz external crystal, requires you to enter the external crystal frequency, as shown in Figure 12.: Main oscillator clocks selection, step 1. Figure 12. Main oscillator clocks selection, step 1 The frequency must be in the range from 4 to 25 MHz. Note: If the STR91x provides clock to the external Ethernet PHY interface device, the frequency must be 25 MHz. Otherwise, a separate clock is needed for the PHY. The PLL can be used to generate the desired master clock frequency used by the CPU and various peripherals. Note: 1 The maximum master clock output is 96 MHz. 2 When using USB, the master clock frequency should be either 48 MHz or 96 MHz, unless an external USB clock is provided. Selecting the PLL clock, requires you to enter the external crystal frequency and the PLL frequency, as shown in Figure 13.: PLL clocks selection, step 1. |
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