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PD64A датащи(PDF) 13 Page - Renesas Technology Corp |
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PD64A датащи(HTML) 13 Page - Renesas Technology Corp |
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13 / 66 page ![]() 11 µPD64A, 65 Data Sheet U14380EJ3V0DS00 Figure 2-4. Data Memory Configuration 2.6 Data Pointer (DP): 11 Bits The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents. The lower 8 bits of the ROM address are specified by R0 of the data memory; and the higher 3 bits by bits 4, 5, and 6 of the P3 register (CR0). After reset, the pointer contents become “000H”. Figure 2-5. Data Pointer Configuration Note Set DP10 of the µPD64A to 0. 2.7 Accumulator (A): 4 Bits The accumulator, which is a register consisting of 4 bits, plays a leading role in performing various operations. After reset, the accumulator contents are left undefined. Figure 2-6. Accumulator Configuration A3 A2 A1 A0 A R00 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1 DP0 R10 R0 b4 b5 P3 register P3 DP10 b6 Note R1n (Higher 4 bits) R0n (Lower 4 bits) R0 DP (refer to 2.6 Data Pointer (DP)) R10 R00 R11 R01 R12 R02 R13 R03 R14 R04 R15 R05 R16 R06 R17 R07 R18 R08 R19 R09 R1A R0A R1B R0B R1C R0C R1D R0D R1E R0E R1F R0F R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF ASR (refer to 2.3 Address Stack Register (ASR (RF))) |
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