ST9 datasheet(52/146 Pages) STMICROELECTRONICS

номер детали	ST9

подробное описание детали	USER GUIDE

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ST9 USER GUIDE

The simplified block diagram is the following:

Figure 20

. External Interrupts Simplified Block Diagram

3.4.3.2 Top-Level Interrupt

The Top Level Interrupt can have two sources: either the NMI pin, or the watchdog end-of-

count(5). This interrupt level has a special feature that allows you to mask it like any other in-

terrupt, or to make it a real non-maskable interrupt. For this, the TLNM bit (see Figure 21) can

remove the effect of the mask. Once set, it cannot be reset, thus preventing this interrupt from

(5) See Section 4.3 on the Watchdog Timer.

External Interrupt pin

(INT0 to INT7)

Edge trigger event

selection: one bit of EITR

Internal/External

source selection

One bit of

EIPR

Pending Bit

One bit of

EIMR

External interrupt

priority level

Current priority

level (CPL)

Interrupt to

the core

Bit IEN of CICR

Interrupt enable

Only for:

A0: INT0 or WDT interrupt

B0 INT2 or SPI interrupt

Internal interrupt

Priority

Comparator

(Device dependent)

A detailed block diagram

is provided in Section 7

Mask Bit

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