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AN3114 датащи(PDF) 40 Page - STMicroelectronics |
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AN3114 датащи(HTML) 40 Page - STMicroelectronics |
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40 / 43 page ![]() LCD segment drive firmware AN3114 40/43 Doc ID 16829 Rev 3 5.2.1 LCD controller setup The following steps are recommended to configure the LCD controller: 1. Enable the LCD clock. 2. Configure the RTC clock source. 3. Configure the duty ratio and the bias. 4. Configure the frame frequency in the operating frequency range of the LCD glass, that is between 20 and 85 Hz. 5. Configure the voltage source. 6. Configure the port mask registers according to the pins used as segment lines. 7. If the internal voltage source is selected, then adjust the contrast using the contrast bits. 8. If the external voltage source is selected, then adjust the contrast using the dead time bits. 9. The contrast can be adjusted also using the pulse on duration bits. 10. Enable the LCD controller. In this application, the LCD controller is configured as follows: ● LCD clock source frequency fLCDCLK = LSE frequency = 32.768 KHz ● Prescaler factor = 2 ● Divider factor = 18 (16 + 2) ● Mode = 1/4 Duty, 1/3 Bias applies to medium density STM8L152xx devices (PD-878 LCD Glass) and Mode = 1/8 Duty, 1/4 Bias applies to high density STM8L152xx/STM8L162xx devices (HXO5002B custom LCD glass) ● LCD clock frequency The LCD clock frequency, fframe, is given by the equation below: As a result, if fck_div equals 228 Hz, fframe = 57Hz for PD-878 LCD glass and fframe = 28.5 Hz for custom LCD glass HXO5002B. f frame f ck_divxduty f LCDCLK 2 PS x16 DIV + () ------------------------------------------xduty == |
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