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AN3057 датащи(PDF) 12 Page - STMicroelectronics |
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AN3057 датащи(HTML) 12 Page - STMicroelectronics |
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12 / 15 page ![]() Recommendations when developing the M24LRxx application software AN3057 12/15 Doc ID 16239 Rev 4 Application hardware architecture The application Master should control the I²C bus lines and the power supply line so as to keep full control of the M24LRxx. Figure 10 shows a typical hardware schematic. Figure 10. Optimal hardware schematic of an M24LRxx application This type of hardware architecture is optimal in applications where power saving is a key feature (like portable applications supplied from a battery). The supply voltage can be directly delivered to an ultralow power microcontroller (for instance the STM8L, information available from http://www.st.com/mcu/). This implementation makes it possible to keep the application supply current in the 1 µA range (value of the STM8L supply current when in the Active-Alt mode) and: ● the application saves power when in the Standby mode, as the battery does not supply the standby current to the M24LRxx (40 µA) nor the current through the SDA pull-up resistor ● the application controls the M24LRxx in a safe mode (the VCC pin is supplied by the Master only when an I²C request is being processed) 3.1.3 An I²C request was interrupted A Start condition defines the I²C channel as busy until the completion of the I²C command (Stop condition). Therefore, if, for some uncontrolled reasons, the I²C bus master sends a single Start condition (due to a glitch on the bus or some other unpredictable conditions), the I²C bus might possibly remain busy indefinitely. The resulting I²C busy state inhibits the decoding of any subsequent I²C and/or RF requests. The I²C busy state is reset either by: ● decoding a device select byte different from 1010 XXXXb ● decoding a Stop condition ● the completion of the internal write cycle (tW, triggered by a decoded write instruction) The best way for the I²C bus Master to clear a spurious busy state is to periodically issue a [Start+Stop] sequence. Note: In noisy applications, ST recommends to implement the “9 Start + 1 Stop” sequence described in AN1471 (available from the ST website: www.st.com). I/O SDA SCL VCC VSS M24LRxx I²C bus Master C = 10 nF R=10 Ω VCC Battery VCC Rpull-up ai17545v2 Application master |
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