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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UPD703003A датащи(PDF) 28 Page - NEC |
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UPD703003A датащи(HTML) 28 Page - NEC |
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28 / 40 page  µPD703003A, 703004A, 703025A 28 Data Sheet U13188EJ4V0DS00 (7) Bus hold timing (1/2) Parameter Symbol Conditions 25 MHz Version 33 MHz Version Units MIN. MAX. MIN. MAX. HLDRQ setup time (to CLKOUT ↓) <54> tSHQK 55 ns HLDRQ hold time (from CLKOUT ↓) <55> tHKHQ 55 ns HLDAK delay time from CLKOUT ↑ <56> tDKHA 20 20 ns HLDRQ high-level width <57> tWHQH T + 10 T + 10 ns HLDAK low-level width <58> tWHAL –40 °C ≤ TA ≤ +70°C T – 10 T – 10 ns 70 °C < TA ≤ 85°C T – 12 T – 12 ns Delay time from CLKOUT ↑ to bus float <59> tDKF 20 20 ns Delay time from HLDAK ↑ to bus output <60> tDHAC –3 –3 ns Delay time from HLDRQ ↓ to HLDAK↓ <61> tDHQHA1 (2n + 7.5)T + 20 (2n + 7.5)T + 20 ns Delay time from HLDRQ ↑ to HLDAK↑ <62> tDHQHA2 0.5T 1.5T + 20 0.5T 1.5T + 20 ns Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function. |
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