UPD703003 datasheet(58/82 Pages) NEC

номер детали	UPD703003

подробное описание детали	V853TM 32/16-BIT SINGLE-CHIP MICROCONTROLLER

PDF	82 Pages

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производитель	NEC [NEC]

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µPD703003

Data Sheet U12261EJ2V1DS00

Data Hold Characteristics (TA = –40 to +85

°C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Units

Data hold voltage

VDDDR

STOP mode

1.5

5.5

Data hold current

IDDDR

VDD = VDDDR

–40

°C ≤ TA ≤ +50°C

0.2 VDDDR

µA

°C < TA ≤ 85°C

0.2 VDDDR

200

µA

Power supply voltage rise time

tRVD

200

µs

Power supply voltage fall time

tFVD

200

µs

Power supply voltage hold time

tHVD

0ms

(vs. STOP mode setting)

STOP mode release signal input time tDREL

0ns

Data hold high-level input voltage

VIHDR

Note

0.9 VDDDR

VDDDR

Data hold low-level input voltage

VILDR

Note

0.1 VDDDR

Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/

INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1,

P27/SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/

SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1

Remark TYP. values are reference values for when TA = 25

°C and VDD = 5.0 V.

tHVD

VDD

tFVD

tRVD

tDREL

VDD

VDDDR

RESET (input)

VIHDR

NMI (input)

(Released at falling edge)

VIHDR

VILDR

NMI (input)

(Released at rising edge)

STOP mode setting (fifth clock after PSC register is set)

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