AN2822

High speed internal oscillator trimming

Doc ID 14983 Rev 2

11/19

1.5

Timing of calibration period measurement

The ‘digital filtering technique’ is applied on the TI1 input from TIM3_CC1 (see Figure 2) to

further reduce period measurement uncertainty. This technique includes an event counter,

present on the input capture pin, in which a certain number of TI1 samples with the same

level are needed to validate a transition of the reference timebase. The number of such

pulses and the sampling frequency can be set by bits IC1F[3:0] in the TIM3_CCMR1

transition to be valid. This default value can be changed if needed. This digital filtering

technique causes a delay between TI1 and the IC1 signal. It does not affect the

measurement of HSI pulses per calibration interval (see Figure 5).

Figure 5.

Timing diagram of calibration period measurement

Counter

Register

Value

OVF

TI1

IC1PS

CC

OVL

OVL

OVL

OVL

OVL

Filter Delay

L = 4

CC

OVL