Register description

AN2628

20/27

A.2

CAN control register

CAN1CR (EF00h),

CAN2CR (EE00h)

XBUS

Reset Value: 0001h

15

14

13

12

11

10

987

65432

10

-

-----

--

Test

CCE

DAR

-

EIE

SIE

IE

Init

RW

RW

RW

RW

RW

RW

RW

Table 4.

CAN1CR and CAN2CR registers

Bit

Function

Init

Initialization

’0’: Normal operation.

’1’: Initialization is started.

IE

Module interrupt enable

’0’: Disabled - Module interrupt IRQ_B is always high.

’1’: Enabled - Interrupts will set IRQ_B to LOW. IRQ_B remains low until all pending

interrupts are processed.

SIE

Status change interrupt enable

’0’: Disabled - No Status Change Interrupt will be generated.

’1’: Enabled - An interrupt will be generated when a message transfer is successfully

completed or a CAN bus error is detected.

EIE

Error interrupt enable

‘0’: Disabled - No error status interrupt will be generated.

‘1’: Enabled - A change in the bits BOff or EWarn in the status register will generate

an interrupt.

DAR

Disable automatic retransmission

‘0’: Automatic retransmission of disturbed messages enabled.

‘1’: Automatic retransmission disabled.

CCE

Configuration change enable

‘0’: The CPU has no write access to the bit timing register.

‘1’: The CPU has write access to the Bit Timing register (while Init = one).

Test

Test mode enable

‘0’: Normal operation.

‘1’: Test mode.