Reference design

AN2586

22/28

Doc ID 13675 Rev 7

6

Reference design

6.1

Description

The reference design shown in Figure 14, is based on the STM32F103ZE(T6), a highly

RISC CPU core with 512 Kbytes of embedded Flash memory and up to 64 Kbytes of high-

speed SRAM

.

This reference design can be tailored to any other STM32F10xxx device with different

package, using the pins correspondence given in Table 6: Reference connection for all

packages.

6.1.1

Clock

Two clock sources are used for the microcontroller:

●

LSE: X1– 32.768 kHz crystal for the embedded RTC

●

HSE: X2– 8 MHz crystal for the STM32F10xxx microcontroller

Refer to Section 2: Clocks on page 11.

6.1.2

Reset

The reset signal in Figure 14 is active low. The reset sources include:

●

Reset button (B1)

●

Debugging tools via the connector CN1

Refer to Section 1.3: Reset and power supply supervisor on page 8.

6.1.3

Boot mode

The boot option is configured by setting switches SW2 (Boot 0) and SW1 (Boot 1). Refer to

Section 3: Boot configuration on page 15.

Note:

In low-power mode (more specially in Standby mode) the boot mode is mandatory to be

able to connect to tools (the device should boot from the SRAM).

6.1.4

SWJ interface

The reference design shows the connection between the STM32F10xxx and a standard

JTAG connector. Refer to Section 4: Debug management on page 17.

Note:

It is recommended to connect the reset pins so as to be able to reset the application from

the tools.

6.1.5

Power supply

Refer to Section 1: Power supplies on page 6.