LTC4255

6

4255f

FAULT (Pin 1): Open-Drain FAULT Output. Pulls low when

a short-circuit or open circuit fault occurs. The signal can

be used to generate a fault condition interrupt to the host

controller eliminating the need for continuous software

polling.

SCL (Pin 2): Serial Interface Clock Input. It requires a

resistor or current source that pulls up to a supply that is

less than 6V.

SDA (Pin 3): Serial Interface Data Input and Output. It

requires a resistor or current source that pulls up to a

supply that is less than 6V.

AD0-4 (Pins 4,5,6,7,8): Serial Interface Address Inputs.

Connect to DGND for a low, float or connect to 3.3V or 5V

supply for a high.

RELAY1-4 (Pins 9,10,11,12): Relay Driver Outputs. Open

collector capable of sinking 50mA to within 0.3V of DGND.

An internal 18V clamp to DGND will protect the part when

the relay is turned off.

DGND (Pin 13): Digital Ground. Return for digital logic and

relay drivers. Must be within

±5V of AGND.

and relay drivers. Bypass with a 0.1

µF capacitor to DGND.

AGND (Pin 15): Analog Ground.

SENSE1-4 (Pins 16,19,23,26): Current Sense Inputs.

Monitors the FET current with a sense resistor placed

PI FU CTIO S

sense resistor reaches the short-circuit sense voltage, the

GATE pin voltage will be lowered to maintain a constant

current in the FET. At the same time, the current limit timer

will be started. If the short-circuit condition persists for the

duration of the current limit timer period, the FET will be

turned off. The short-circuit sense voltage is lowered to

reduce the FET power dissipation when the voltage at the

associated OUT pin is within 18V of AGND.

If the open-circuit enable bit is set and the voltage across

the sense resister remains below the open-circuit sense

then the FET will be turned off.

GATE1-4 (Pins 17,20,24,27): Gate Drive Outputs. When

the FET is turned on, a 50

µA pull-up current source is

connected to the pin. The gate voltage is clamped to

GATE pin voltage will be driven to a lower voltage to

maintain a constant current in the FET.

OUT1-4 (Pins 18,21,25,28): Output Voltage Monitor In-

puts. A current limit foldback feature limits the power

dissipation in the FET by reducing the short-circuit current

when the voltage at the OUT pin is between AGND and

AGND – 18V. The Power_OK bit is set when the voltage