Amplifier design

AN1229

2/7

1

Amplifier design

1.1

Input matching network

Typical input gate-to-gate impedance of SD2932 at 100 MHz is Zin = Rs + jXs = 2 - 2.6 j,

and can also be expressed as the combination of parallel resistance and reactance using

the following formulas:

Equation 1

Equation 2

Therefore, in order to achieve good input matching performances over the frequency range

88-108 MHz the unbalanced 50

Ω is to be transformed into an impedance with a value as

close as possible to Rp of 5.38

Ω.

From the circuit schematic given in Figure 6 , we can see that the input matching network is

based on a two section balun (1:1 balun in cascade with a 9:1 balun transformer) which

transforms the unbalanced 50

Ω to a balanced 5.56 Ω (2 x 2.78 Ω / 9:1 ratio). The first

section, a 5" long - 50

Ω coaxial cable and the second section, a two 3.9" long - 25 Ω flexible

coaxial cables with ferrite core NEOSIDE, are connected as described: a 10 nH inductor

(L1) is connected between the two gates to compensate SD2932 input parallel reactance

Xp.

1.2

Input matching network tuning

Figure 1.

Input Impedance of 1:1 balun in cascade with 4:1 balun

Rp

Rs

1

Xs

Rs

-------

⎝⎠

⎛⎞

2

+

•

5.38

Ω

=

=

X

P

R

P

X

S

R

S

-------

⎝⎠

⎛⎞

⁄

4.14j

Ω

–

=

=

0

50

100

150

200

250

300

350

Frequency (MHz)

-35

-30

-25

-20

-15

-10