Example of a quadruplex LCD with ST72F321B

AN1048

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Figure 8.

Hardware Connection Diagram

The LCD Timing is generated by the TimerA output compare interrupt. Each cycle consists

of four phases, one for each backplane. Each COM line generates its waveform during the

corresponding phase e.g. COM1 line during phase1. During other phases it remains at level

1. Active time

2. Dead time

During the Active time, the segment lines and COM lines are used to drive the LCD. During

dead time Segment and COM lines are used to tune the contrast.

Vcc

PC0-C3

PA0-A5

PB0-B7

PD0-D7

PF0-F7

Common Lines

Segment Lines

LCD GLASS

ST72F321B

6

8

8

8

Network Resistors

56K

56K

PE6-E7

2