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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UPD61P24CS датащи(PDF) 12 Page - NEC |
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UPD61P24CS датащи(HTML) 12 Page - NEC |
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12 / 36 page  µPD61P24 12 12. PORT REGISTER (P×) KI/O, KI, and the control register are handled as port registers. The table below shows the relations between the port registers and pins. Table 12-1. Relations between Port Registers and Pins Pin Input Mode Output Mode Name Read Write Read Write On Reset KI/O Pin status Output latch Pin status Output latch Undefined [input mode, output latch] KI Pin status – – – Input mode S-IN Pin status is read by RL A instruction when D0 of P1 register = 1. High impedance (D0 of P1 register = 0) P 10 P 11 P 12 P 00 P 01 P 02 K I/O7-4 K I/O3-0 P 0 P 1 P 2 Control register (H) Control register (L) K I3-0 P1 × (H) P0 × (L) |
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