LTC1287

13

1287fa

S

APPLICATI

I FOR ATIO

Figures 13 and 14 show examples of both adequate and

poor settling. Using a slower CLK will allow more time

for the reference to settle. Even at the maximum CLK

rate of 500kHz most references and op amps can be

made to settle within the 2

µs bit time. For example an

LT1790 with a 4.7

µF bypass capacitor will settle

adequately.

Reduced Reference Operation

The effective resolution of the LTC1287 can be in-

creased by reducing the input span of the converter.

The LTC1287 exhibits good linearity over a range of

reference voltages (seeTypical Performance Charac-

teristics curves of Change in Linearity vs Reference

Voltage). Care must be taken when operating at low

the resulting higher accuracy requirement placed on

the converter. Offset and Noise are factors that must be

The offset of the LTC1287 has a larger effect on the

output code when the A/D is operated with a reduced

reference voltage. The offset (which is typically a fixed

voltage) becomes a larger fraction of an LSB as the size

of the LSB is reduced. The Typical Performance Charac-

teristics curve of Unadjusted Offset Error vs Reference

Voltage shows how offset in LSBs is related to reference

0.1mV, which is 0.2LSB with a 2.5V reference becomes

0.4LSB with a 1.25 reference. If this offset is unaccept-

able, it can be corrected digitally by the receiving system

or by offsetting the –IN input to the LTC1287.

The total input referred noise of the LTC1287 can be

reduced to approximately 200

µV peak-to-peak using a

ground plane, good bypassing, good layout techniques

and minimizing noise on the reference inputs. This

noise is insignificant with a 2.5V reference input but will

become a larger fraction of an LSB as the size of the LSB

is reduced. The Typical Performance Characteristics

Figure 14. Poor Reference Settling Can Cause A/D Errors

Figure 13. Adequate Reference Settling

HORIZONTAL: 1

µs/DIV

HORIZONTAL: 10

µs/DIV

conversion (every CLK cycle) a capacitive current spike

will be generated on the reference pin by the A/D. These

current spikes settle quickly and do not cause a prob-

lem. If slow settling circuitry is used to drive the

reference input, take care to insure that transients

caused by these current spikes settle completely during

each bit test of the conversion.

Figure 12. Reference Input Equivalent Circuit

8pF – 40pF

LTC1287

REF+

EVERY CLK CYCLE

14

13

GND

LTC 1287 F12