LTC1099 datasheet(8/16 Pages) LINER

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LTC1099

HOLD

T+

T–1

T–2

T+

T–1 T–2

STROBE

SAMPLE

(+)

(–)

VIN

MS TAP

DAC

0.5 LSB

LS TAP

VIRTUAL

GROUND

C1 = C2

1099 F06

FUNCTIONAL DESCRIPTIO

also that variations in the bias voltage with time and

temperature will also be rejected. In this state, C1 charges

to VIN. When TZ opens, VIN is held on C1.

The next step is the first comparison — the MS-Flash. TZ

and T+ are opened and T–1 is closed. The equation for each

comparator is:

VIN + 0.5LSB – MSTAP = 0V

There are 16 identical comparators each tied to the tap on

a 16 resistor ladder. The MS tap voltages vary from VREF

to 0V in 16 equal steps of VREF/16.

Notice that capacitor C2 adds 0.5LSB to VIN. This offsets

the converter transfer function by 0.5LSB, equally distrib-

uting the 1LSB quantization error to

±0.5LSB.

The outputs of the 16 comparators are temporarily latched

and drive the 4-bit DAC directly without need of decoding.

This holds the DAC output constant for the next step — the

LS conversion. The LS conversion is started when T–1 is

opened and T–2 is closed. Capacitor C1 subtracts the 4-bit

DAC approximation from VIN and inputs the difference

charge to the virtual ground node. The equation for each

comparator is:

VIN + 0.5LSB – VDAC – LSTAP = 0V

The 4-bit DAC approximation is input to all 16 compara-

tors. The LS tap voltages are converted to charge by

capacitor C2. LS taps vary from VREF/16V to 0V in 16 equal

steps of VREF/256. The comparators look at the net charge

on the virtual ground node to perform the LS-Flash con-

version. When this conversion is complete, the four LSBs

along with the four MSBs are transferred to the output

latches. In this way, all eight outputs will change

simultaneously.

Figure 6. Six Input Switched Capacitor Comparator

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