LT1640L datasheet(12/16 Pages) LINER

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LT1640L/LT1640H

1640lhfb

The new threshold voltage when the input moves from low

to high is:

UV LH

UVH

•••

•









where VUVH is typically 1.243V.

The new threshold voltage when the input moves from

high to low is:

UV HL

UVL

GATE

•••

•

–•

















where VUVL is typically 1.223V.

The new hysteresis value will be:

HYS

UVHY

GATE

















•••

•

With R1 = 562k, R2 = 16.9k and R3 = 1.62M, VGATE = 13.5V

and VUVHY = 20mV, the undervoltage threshold will be 43V

(from low to high) and 37.6V (from high to low). The

hysteresis is 5.4V. A separate resistor divider should be

used to set the overvoltage threshold given by:

APPLICATIONS INFORMATION

OVH









With R4 = 506k, R5 = 8.87k and VOVH = 1.223V, the

overvoltage threshold will be 71V.

PWRGD/PWRGD Output

The PWRGD/PWRGD output can be used to directly en-

able a power module when the input voltage to the module

is within tolerance. The LT1640L has a PWRGD output for

modules with an active low enable input, and the LT1640H

has a PWRGD output for modules with an active high

enable input.

When the DRAIN voltage of the LT1640H is high with

respect to VEE (Figure 11), the internal transistor Q3 is

turned off and R7 and Q2 clamp the PWRGD pin one diode

drop (

≈0.7V) above the DRAIN pin. Transistor Q2 sinks

the module’s pull-up current and the module turns off.

When the DRAIN voltage drops below VPG, Q3 will turn on,

shorting the bottom of R7 to DRAIN and turning Q2 off.

The pull-up current in the module then flows through R7,

pulling the PWRGD pin high and enabling the module.

VEE

VDD

LT1640H

SENSE

GND

– 48V

GATE

1640 F11

PWRGD

DRAIN

VEE

6.5k

–

VPG

ACTIVE HIGH

ENABLE MODULE

VOUT

–

VIN

–

ON/OFF

GND

(SHORT PIN)

* DIODES INC. SMAT70A

× 1N4148

–

Figure 11. Active High Enable Module

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