DocID027168 Rev 1

5/18

UM1839

Hardware description and configuration

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Table 3. Jumper descriptions

Name

Type

Function

JP1, JP2 Configuration jumpers IN- and IN+ sharing in 2-board configuration.

JP3

Configuration jumper

For SPI daisy chaining in 2-board configuration.

JP4

Configuration jumper

To feed the STGAP1S with VDD voltage coming from the µC

board.

JP5

Configuration jumper

To connect VL and GNDISO if an optional negative power supply

VL is not used.

JP6

Configuration jumper

To connect VDD and Vreg when working with VDD = 3.3 V.

JP7

Configuration jumper

To bypass shunt resistors when SENSE is not used.

1. Input signals logic levels shall be coherent with VDD voltage (3.3\5 V).

Operating voltage

Supply voltage source

Jumper configurations

VDD = 5 V

External power supply

(from J6)

JP4 = OPEN

JP6 = OPEN

VDD = 3.3 V

External power supply

(from J6)

JP4 = OPEN

JP6 = CLOSED

VDD = 3.3 V

µC supply voltage

(from J4)

JP4 = CLOSED

JP6 = CLOSED

Table 5. Jumper configurations for VL power supply

Operating voltage

Supply voltage source

Jumper configurations

-10 V ≤ VL < 0 V

External power supply (J2)

JP5 = OPEN

VL not used

VL = GNDISO

JP5 = CLOSED

Table 6. Jumper configurations for SPI and input signals settings

(single EVALSTGAP1S)

Name

Function

Jumper configurations

JP1

IN+ connection to the optional slave

EVALSTGAP1S

DON'T CARE

JP2

IN-/DIAG2 connection to the optional

slave EVALSTGAP1S

DON'T CARE

JP3

Connects the SDO to the µC

CLOSED

SENSE function

Jumper configurations

Used

JP7 = OPEN

Not used

1. This configuration is preferred (but not mandatory) to avoid dissipating power on shunt resistors.