Example IV

UM1763

12/16

DocID026335 Rev 1

Figure 5. SMED 0 state machine

The input voltage measure is performed by the ADC at a given frequency set by the system

timer. The STMR interrupt handler performs the regulation loop reading the Vin sampled

value and computing the PWM0 according to the behavior described above.

The main code properly configures the I/O pins, the ADC, the SMED 0. It also sets the

STMR to work at a frequency that's a fraction of the HSI (16 MHz). In particular a frequency

of 10 KHz has been chosen to generate interrupts. Nothing more is needed as the SMED 0

will autonomously regulate the PWM0 to follow the behavior specified above.

Now when the input voltage falls off of the [200 mV; 1 V] range, the SMED 0 stops. Possible

evolution of this example could be modifying the firmware so that outcoming 1 V, the SMED

0 keeps going on keeping the PWM duty cycle constant. This “protection” is handled using

the same loop regulation or use the input event (CP0 and DAC0 for example) directly on the

SMED.