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AN4506 датащи(PDF) 35 Page - STMicroelectronics |
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AN4506 датащи(HTML) 35 Page - STMicroelectronics |
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35 / 47 page ![]() AN4506 First-in first-out (FIFO) buffer DocID026442 Rev 2 35/47 6.2.3 FIFO source register (0x2F) This register is updated at every ODR and provides information about the FIFO buffer status. FTH bit is set high when FIFO content exceeds FIFO threshold. OVRN bit is set high when FIFO buffer is full; this means that the FIFO buffer contains 32 unread samples. At the following ODR a new sample set replaces the oldest FIFO value. The OVRN bit is reset when the first sample set has been read. EMPTY flag is set high when all FIFO samples have been read and FIFO is empty. FSS[4:0] field always contains the current number of unread samples stored in the FIFO buffer. When FIFO is enabled, this value increases at ODR frequency until the buffer is full, whereas, it decreases every time that one sample set is retrieved from FIFO. Register content is updated synchronous to the FIFO write and read operation. The FIFO threshold flag, the FIFO overrun and FIFO empty event can be enabled to generate a dedicated interrupt on the DRDY/INT2 pin by configuring CTRL3. INT2_FTH bit drives FIFO threshold flag (FTH) on the DRDY/INT2 pin INT2_ORun bit drives Overrun event (OVRN) on the DRDY/INT2Y pin INT2_Empty bit drives Empty event (EMPTY) on the DRDY/INT2 pin. If one or more bits are set to “1”, the DRDY/INT2 pin status is the logical OR combination of the three signals. Table 31. FIFO_SRC register b7 b6 b5 b4 b3 b2 b1 b0 FTH OVRN EMPTY FSS4 FSS3 FSS2 FSS1 FSS0 Table 32. FIFO_SRC_REG behavior assuming FTH[4:0] = 15 FTH OVRN EMPTY FSS[4:0] Unread FIFO samples Timing 0 0 1 00000 0 t0 0 0 0 00001 1 t0 + 1/ODR 0 0 0 00010 2 t0 + 2/ODR ... ... ... ... ... ... 0 0 0 01111 15 t0 + 15/ODR 1 0 0 10000 16 t0 + 16/ODR ... ... ... ... ... ... 1 0 0 11110 30 t0 + 30/ODR 1 0 0 11111 31 t0 + 31/ODR 1 1 0 11111 32 t0 + 32/ODR Table 33. CTRL3 (0x22) b7 b6 b5 b4 b3 b2 b1 b0 XXXXX INT2_FTH INT2_ORun INT2_Empty |
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