AN4382 datasheet(22/70 Pages) STMICROELECTRONICS

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ZVS LC resonant stage description

AN4382

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DocID025437 Rev 1

4.2

Protections

The STLUX385A offers several levels of protections:

Output undervoltage protection (UVP): prevents the LC resonant stage from operating

when it's input voltage, i.e. the PFC output capacitor voltage, is at very low voltage.

When an UVP condition arises, the STLUX385A stops the switching activity on the LC

stage until the PFC voltage returns above an acceptable range.

No load: prevents the LC stage to operate while there is no LED string connected. This

protection preserves the resonant output capacitors from being damaged due to

overcharge. When the output capacitors voltage reaches a threshold, the STLUX385A

disables the resonant activity within 50 ns.

Brownout protection: When the AC input voltage drops under 90 V the resonant stage

is disabled at the same time as the PFC.

Short-circuit protection: the STEVAL385LEDPSR demonstration board architecture

ensures that the output current in a short-circuit condition is always limited to the actual

current level configured by the serial, DALI or 0 - 10 interface.

4.3

ZVS LC resonant stage implementation on STLUX385A

Similarly to the PFC stage, the LC resonant stage is driven by the SMED technology

implemented by the STLUX385A. In particular, one SMED is used to control the half bridge

high-side while another SMED controls the low-side. Using two SMEDs gives the

STLUX385A full control over the half bridge conduction and deadtimes.

An additional PWM (SMED2) is used to feed a low-pass filter and generate a high precision

signal with 12-bit resolution. The signal is monitored via ADC1 and continuously adjusted to

compensate for the external circuit tolerance.

Table 3

shows the STLUX385A inputs and outputs used to control the resonant stage.

Table 3. List of STLUX385A pins used by the ZVS LC stage

Description

PWM0

PWM driving the half bridge low side MOSFET. The output is generated by SMED0.

PWM1

PWM driving the half bridge high side MOSFET. The output is generated by SMED1.

PWM2

Used to generate a high precision reference with 12 bit resolution. PWM2 is the input to an external low-

pass filter which generates the reference.

PWM3

Used for synchronization.

DIGIN5 Used for synchronization.

CPP3

Monitors the current on half bridge.

CPM3

Input of the high precision reference

CPP1

Monitor for no load conditions. The half bridge operation is stopped when there is no load.

ADC1

Monitor for the high precision reference.

ADC2

Samples the scaled reflected voltage from the transformer.

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