8

LTC4557

4557f

OPERATIO

Activation/Deactivation

Activation and deactivation sequencing is handled by

built-in circuitry. The activation sequence is initiated by

bringing the ENABLE pin HIGH. The activation sequence is

outlined below:

1. The RST, CLK and I/O pins are held LOW.

channels are enabled.

4. The clock channel is enabled on the rising edge of the

second clock cycle after the I/O pin is enabled.

The deactivation sequence is initiated by bringing the

ENABLE pin LOW. The deactivation sequence is outlined

below:

1. The reset channel is disabled and RST is brought LOW.

2. The clock channel is disabled and the CLK pin is brought

LOW two clock cycles after ENABLE is brought LOW. If

the clock is not running, the clock channel will be

disabled approximately 9

µs after the ENABLE pin is

brought LOW.

3. The I/O channel is disabled and the I/O pin is brought

LOW approximately 9

µs after the ENABLE is brought

LOW.

The activation or deactivation sequences will take place

every time a card socket is enabled or disabled.

Fault Protection

short-circuit faults. While there are no logic outputs to

indicate that a fault has occurred, these pins will be able

to tolerate the fault condition until it has been removed.

tion circuitry which will limit the current available to the

90mA (typ) before the output voltage is reduced.

The CLKA,B pins are designed to tolerate faults by reduc-

ing the current drive capability of their output stages. After

a fault is detected by the internal fault detection logic, the

logic waits for a fault detection delay to elapse before

reducing the current drive capability of the output stage.