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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AN3308 датащи(PDF) 42 Page - STMicroelectronics |
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AN3308 датащи(HTML) 42 Page - STMicroelectronics |
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42 / 52 page  First in first out (FIFO) buffer AN3308 42/52 Doc ID 18198 Rev 1 9.2.3 FIFO source register (0x2F) This register is updated at every ODR and provides information about the FIFO buffer status. ● WTM bit is set high when FIFO content exceeds watermark level. ● OVRN bit is set high when FIFO buffer is full, this means that the FIFO buffer contains 32 unread samples. At the following ODR a new sample set replaces the oldest FIFO value. The OVRN bit is reset when the first sample set has been read. ● EMPTY flag is set high when all FIFO samples have been read and FIFO is empty. ● FSS[4:0] field always contains the current number of unread samples stored in the FIFO buffer. When FIFO is enabled, this value increases at ODR frequency until the buffer is full, whereas, it decreases every time that one sample set is retrieved from FIFO. Register content is updated synchronous to the FIFO write and read operation. The watermark flag and FIFO overrun event can be enabled to generate a dedicated interrupt on the INT1 pin by configuring CTRL_REG3. ● I1_WTM bit drives watermark flag (WTM) on the INT1 pin. ● I1_OVRN bit drives overrun event (OVRN) on the INT1 pin. Table 37. FIFO_SRC_REG b7 b6 b5 b4 b3 b2 b1 b0 WTM OVRN EMPTY FSS4 FSS3 FSS2 FSS1 FSS0 Table 38. FIFO_SRC_REG behavior assuming FTH[4:0] = 15 WTM OVRN EMPTY FSS[4:1] Unread FIFO samples Timing 0 0 1 00000 0 t0 0 0 0 00001 1 t0 + 1/ODR 0 0 0 00010 2 t0 + 2/ODR ... ... ... ... ... ... 0 0 0 01111 15 t0 + 15/ODR 1 0 0 10000 16 t0 + 16/ODR ... ... ... ... ... ... 1 0 0 11110 30 t0 + 30/ODR 1 0 0 11111 31 t0 + 31/ODR 1 1 0 11111 32 t0 + 32/ODR Table 39. CTRL_REG3 (0x22) b7 b6 b5 b4 b3 b2 b1 b0 X X X X X I1_WTM I1_OVRN X |
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