AN2478

Normal mode functionality

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Normal mode functionality

During normal mode status, the serial data present on the SDI pin is transferred to the shift

register during the CLK rise time signal transition. After 8 CLK pulses for the STP08DP05,

or 16 CLK pulses for the STP16DP05, the data loaded on the SDI pin will be shifted to the

SDO pin with a typical delay of 15 ns (depending on the clock). This delay guarantees the

correct synchronization of the CLK and SDI signals if two or more devices are cascaded.

The data present in any register can be transferred to the respective latch when the Latch -

Enable (LE/DM1) is "high" (serial to parallel conversion). After this step, data is transferred

to the outputs by the output enable (OE/DM2) which turns ON the LEDs at the current set by

the external resistor. It is also possible to use the OE/DM2 pin to modify the output ON/OFF

duty cycle. This allows an optimization of dimming when two or more devices are used.

Figure 2.

Typical functionality in normal mode

The signals shown on the plot are:

●

CLK signal (CH1)

●

OE/DM2 signal (CH2)

●

Vout level (CH3)

●

OutputN (CH4) which turn ON and OFF according to the OE pulse

Under specific applicative conditions, where it is necessary to transfer data directly to the

outputs without the OE/DM2 signal (always "low"), the LE/DM1 is synchronized with a CLK

signal that transfers the shift register data to the specific output as reported in the following

plots.