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AN2603 датащи(PDF) 16 Page - STMicroelectronics

номер детали AN2603
подробное описание детали  ST1S09 high efficiency synchronous buck converter
PDF  23 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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Recommendations on board usage
AN2603
16/23
Doc ID 13778 Rev 3
The resistors in Table 1 provide a suitable compromise in terms of current consumption and
minimum output voltage. For output voltages close to the feedback voltage, we suggest to
add a very small capacitor in parallel with R1 in the range of 10 pF. Or, as an alternative, we
suggest to increase the current in the resistor divider by decreasing the R1 and R2 value.
4.1.1
Inductor selection
Due to the high frequency (1.5 MHz) it is possible to use very small inductor values. In this
board the device was tested with inductors in the range of 1 µH to 10 µH, with very good
efficiency results (see below plot).
As the device is able to provide an operative output current of 2 A, The use of inductors
capable of managing at least 3 A is strongly recommended.
4.1.2
Capacitor selection
It is possible to use any X5R or X7R ceramic capacitor:
●
C1 = 4.7 µF (ceramic) or higher.
●
C2 = 22 µF (ceramic) or higher. It is possible to put several capacitors in parallel in
order to reduce the equivalent series resistance and improve the ripple present in the
output voltage.
4.2
Layout considerations
Due to the high switching frequency and peak current, the layout is an important design step
for all switching power supplies. If the layout is not done carefully, important parameters
such as efficiency and output voltage ripple could be compromised.
Short, wide traces must be implemented for main current and for power ground paths as
showed in bold in Figure 13. The input capacitor must be placed as close as possible to the
device pins as well as the inductor and output capacitor.
It is very important to connect the two input pins 4 mm far from the device, it avoids noise
inside the control circuit, coming from the power switch, as shown in Figure 9.
A common ground node minimizes ground noise, as shown in Figure 13. The exposed pad
of the package must be connected to common ground node.
Figure 13.
Layout considerations
VFB
SW
VIN_A
VIN_SW ST1S09
1
5
4
3
R1
R2
L1
Vout
C2
6
C1
GND
Vin
2
GND



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