AN2381 datasheet(45/47 Pages) STMICROELECTRONICS

45 / 47 page

AN2381

Application information

45/47

In particular the DataReady signal, stored in STATUS_REG(3), which indicates when a new

set of acceleration data is ready, is made available by setting DRDY bit to 1 and IEN bit to 0,

while the interrupt signal is carried out when IEN bit is set to 1. Being the pad shared for the

both DataReady and Interrupt, one signal at a time may be generated by the device. In case

both DRDY and IEN are set to 1, the pad will generate the Interrupt signal which is given an

higher priority.

Figure 17.

Interrupt and DataReady Signal Generation Block Diagram

In particular data-ready (RDY) signal rise to 1 when a new set of acceleration data has been

generated and it is available for reading. The signal is reset after all the enabled channels

are read through the serial interface.

Figure 18.

Data Ready Signal

6.10

Using the external clock

The device provides the capability to drive the internal circuitry through an external clock. In

order to switch to the external clock it is necessary to set to 1 the ECK bit stored inside

CTRL_REG3. The external clock must have a frequency of 1.045 MHZ (+/-10%) and a duty

cycle of 50%.

Free-Fall,

Wake-Up

Interrupt

Direction

Detector

Interrupt

Counter

ODR Clock

ff_wu_duration

Latch

FF_WU_CFG(LIR)

Generator

DD_CFG(LIR)

DD_CFG(IEND)

Interrupt signal

CTRL_REG2(IEN)

DataReady signal

CTRL_REG2(DRDY)

Latch

Pad

DataReady

Signal

Generator

Interrupt Generator

(FF, WU, DD)

IA (DD_SRC)

(FF_WU_SRC)

RDY/INT

RDY

DATA READ

ACCEL DATA

Accel. Sample #(N)

Accel. Sample #(N+1)

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