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AN3372 датащи(PDF) 16 Page - STMicroelectronics |
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AN3372 датащи(HTML) 16 Page - STMicroelectronics |
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16 / 37 page ![]() PFC design rules AN3372 16/37 Doc ID 018625 Rev 1 6 PFC design rules The front-end stage of conventional offline converters, typically consisting of a full-wave rectifier bridge with a capacitor filter, has an unregulated DC bus from the AC mains. The filter capacitor must be large enough to have a relatively low ripple superimposed on the DC level. The current from the mains is a series of narrow pulses with very high amplitude. A consequence of this condition is the distortion of the AC line voltage and a poor utilization of the power system's energy capability. This can be measured considering two parameters: 1. the total harmonic distortion (THD) 2. the power factor (PF) Two methods of controlling a PFC preregulator are currently widely used: 1. the fixed frequency average current mode PWM (FF PWM) 2. the transition mode (TM) PWM (fixed ON-time, variable frequency) In this application the PFC section is realized with a boost converter working in transition mode and digitally controlled. Design criteria of the PFC stage power components are explained. 6.1 Specifications ● Minimum mains voltage (RMS value): Vacmin = 85 V ● Maximum mains voltage (RMS value): Vacmin = 265 V ● Minimum main frequency: fmin = 47 Hz ● Expected bridge efficiency: ηbridge = 95% ● Rated lamp power: Plamp = 70 W ● Rated out power: ● Output current: ● Regulated DC output voltage (DC value): Vout = 410 V ● Maximum output low-frequency Vout ripple: Voutx = 20 V ● PFC minimum switching frequency: fmin = 30 kHz ● Expected PFC efficiency: ηPFC 96% ● Expected Input section efficiency: ηin 99% ● Expected power factor: 0.99. 6.2 Operating conditions ● Expected input power: ● Maximum RMS input current: Pout P lamp η bridge ---------------- 73.6W = = A 18 . 0 V P I out out out = = W 5 . 77 99 . 0 96 . 0 95 . 0 150 P P in PFC Bridge lamp in = ⋅ ⋅ = η ⋅ η ⋅ η = A 92 . 0 99 . 0 85 5 . 77 PF V P I min ac in in = ⋅ = ⋅ = |
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