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AN1301 APPLICATION NOTE

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Provides transmit wave-shaper, receive filters, and adaptive equalizer

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Provides loop-back modes for diagnostic testing

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Builds in Stream Cipher Scrambler/Descrambler and 4B/5B encoder/decoder

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Supports external transmit transformer with turn ratio 1:1

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Supports external receive transformer with turn ratio 1:1

3.0 DESIGN AND LAYOUT GUIDELINES

3.1 General Guidelines

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Verify that all components meet application requirements.

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Design in filters for the analog power circuits.

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Use bulk capacitors (10-22uF) between the power and ground planes to minimize switching noise, par-

ticularly near high-speed busses (>25 MHz).

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Use an ample supply of 0.1uF decoupling capacitors to reduce high-frequency noise on the power and

ground planes.

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Use a single analog power and ground plane for multiple devices. Keep ferrite bead currents under 65%

of the rated load

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Avoid breaks in the ground plane, especially in areas where it is shielding high-frequency signals.

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Keep power and ground noise levels below 50mV

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Keep high-speed signals out of the area between STE100P and the magnetics

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Ensure that the power supply is rated for the load and that output ripple is minimal (<50mV)

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Route high-speed signals next to a continuous, unbroken ground plane.

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Provide impedance matching on long traces to prevent reflections.

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Do not route any digital signals between the STE100P and the RJ-45 connectors at the edge of the

board

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It is recommended to fill in unused areas of the signal planes with solid copper and attach them with

vias to a Vcc or ground plane that is not located adjacent to the signal layer.

3.2 Differential Signal Layout Guidelines

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Route differential pairs close together and away from everything else

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Keep both traces of each differential pair as close to the same length as possible.

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Avoid vias and layer changes

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Keep transmit and receive pairs away from each other. Run orthogonally, or separate with a ground

plane layer.

3.3 Power and Ground

In order to obtain high speed communications design, the power and ground planes may be conceptually divid-

ed into three regions (the analog and digital power planes and the signal ground plane)

The analog power region extends from the magnetics back to the STE100P, whereas the digital power region

extends from the MII interfaces of the STE100P through the rest of the board. Only components and signals

pertaining to the particular interface should be placed or routed through each respective region. The digital sec-

tion supplies power to the digital Vcce/i pin and to the external components. The analog section supplies power

to Vcca pins of the STE100P.

The signal ground region is one continuous, unbroken plane that extends from the magnetics through the rest