SPI communication flow

TN0897

12/28

Doc ID 023176 Rev 2

2.3.1

Global error flag definition

The <Global Error Flag> (GEF) is a diagnosis information which is transmitted with every

communication frame. It indicates that a failure condition has been detected which can be

identified in the Status Registers.

The GEF is composed by a logical OR combination of failures notified in the <Global

Status> register and in device specific Status Registers.

Bits 1, 2 and 3 of the <Global Status> register may be maskable in the <Configuration>

register, i.e. these bits may be excluded from the GEF composition.

The clock monitor counts the number of clock pulses during a communication frame (while

CSN is low). If the number of SCK pulses does not correspond with the frame width

indicated in the <SPI-frame-ID> (ROM address 3EH) the frame is ignored and the

<Communication Error> bit in the <Global Status> register is set.

This safety function is implemented to avoid an unwanted activation of output stages by a

wrong communication frame.

If a communication error is detected during a read operation, the <Communication Error> bit

in the <Global Status> register is set, but the register read is transferred to the SDO pin. If

the number of clock cycles is smaller than the frame width, the data at SDO is truncated. If

the number of clock cycles is larger than the frame width, the data at SDO is filled with ‘0’.

If the frame width is greater than 16 bits, initial Read of <SPI-frame-ID> using a 16 bits

communication sets the <Communication Error> bit of the <Global Status> register. A

subsequent correct length transaction is necessary to correct this bit.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is

recommended.

The SPI Failure Detection identifies a short circuit condition at SDI if all bits within a received

In this case the communication frame is ignored, the device enters the <Fail-Safe Mode>

and the <Fail-Safe> bit in the <Global Status> register is set.