Reset and BAM

TN0108

18/26

Doc ID 15874 Rev 2

Note that the RGM_FERD and RGM_DERD registers are ‘write-once’. For details on a

change that was made to this implementation between Cut 1.1 and Cut 2 devices, see the

following section.

For further details on the FERD and DERD registers, consult the device reference manual.

6.3

Write once protection of reset configuration registers

On Cut 1.1 devices, the RGM_DERD and RGM_FERD registers are configured such that

write-once protection to these registers is provided as a 32-bit block. Thus, any write to the

DERD or FERD register (be it 16-bits or otherwise) will prevent further writes to either

register. The only way to correctly configure this is to write to the DERD and FERD registers

in a single 32-bit write.

On Cut 2 devices, the mechanism has been changed such that the RGM_DERD and

RGM_FERD registers each have their own 16-bit write-once mechanism. This is somewhat

irrelevant, since the DERD register has been set to read-only in Cut 2, however it means

that any attempt to write to DERD will not impact the write-once mechanism for FERD.

Table 17.

Reset event disable via RGM_DERD and RGM_FERD

Register bits

Description

SPC560B Cut 1.1

SPC560B Cut 2

RGM_FERD (Functional Event Reset Disable Register)

D_EXR

Disable External Reset

-

Read only

D_Flash

Disable code or data Flash error reset

•

•

D_LVD45

Disable 4.5 V LVI detected reset

•

•

D_CMU0_FHL

Disable CMU0 Clock higher/lower than ref

•

•

D_CMU0_OLR

Disable Oscillator freq lower than reference

•

•

D_PLL/D_FMPLL

Disable PLL0 fail reset (Cut 1.1)

Disable FMPLL fail reset (Cut 2)

••

D_CHKSTOP

Disable checkstop reset

-

Read only

D_Soft

Disable Software reset

-

Read only

D_Core

Disable Core reset

•

•

D_JTAG

Disable JTAG-initiated reset

•

•

RGM_DERD (destructive Event Reset Disable Register)

D_LVD27

-

Read only

D_SWT

•

Read only

D_LVD12_PD1

-

Read only

D_LVD12_PD0

-

Read only