AN2871

On-chip voltage regulator (VREG)

Doc ID 15304 Rev 3

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Figure 1.

External NPN ballast connections configuration for

SPC560P60xx/SPC56AP60xx/SPC560P40xx

Figure 2.

External NPN ballast connections configuration for SPC560P50xx

2.1.2

Circuit architecture

The VREG circuit is a classic emitter-follower configuration controlled voltage source. The

stabilization of the output voltage is achieved using an external capacitance of several µF

(see Section 4).

The BCTRL (voltage regulator external NPN ballast base control pin) controls the current on

decreased to lower the voltage. The gain of the transistor controls the maximum current

The gain should be high enough to allow start-up and low enough to prevent the VREG

becoming instable.

BCTRL

VDD_LV_COR

VDD_HV_REG

BJT

SPC56xx

BCTRL

VDD_LV_COR

VDD_HV_REG

BJT

SPC56xx