Register description

AN2341

20/26

A.3

CAN status register

CAN1SR (EF02h),

CAN2SR (EE02h)

XBUS

Reset Value: 0000h

15

14

13

12

11

10

98

765

43

210

--

---

--

-

BOff

EWarn EPass

RxOk

TxOk

LEC

RR

R

RW

RW

RW

Table 5.

CAN1SR and CAN2SR registers

Bit

Function

LEC

Last error code (Type of the last error to occur on the CAN bus)

’000’: No error.

’001’: Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a

received message where this is not allowed.

’010’: Form Error: A fixed format part of a received frame has the wrong format.

’011’: AckError: The message this CAN Core transmitted was not acknowledged by

another node.

’100’: Bit1Error: During the transmission of a message (with the exception of the

arbitration field), the device wanted to send a

recessive level (bit of logical value ‘1’),

but the monitored bus value was

dominant.

’101’: Bit0Error: During the transmission of a message (or acknowledge bit, or

active error flag, or overload flag), the device wanted to send a

dominant level (data

or identifier bit logical value ‘0’), but the monitored Bus value was

recessive. During

bus-off recovery this status is set each time a sequence of 11 recessive bits has

been monitored. This enables the CPU to monitor the progression of the bus-off

recovery sequence (indicating the bus is not stuck at

dominant or continuously

disturbed).

’110’: CRCError: The CRC check sum was incorrect in the message received, the

CRC received for an incoming message does not match with the calculated CRC for

the received data.

’111’: Unused. When the LEC shows the value ‘7’, no CAN bus event was detected

since the CPU wrote this value to the LEC.

TxOk

Transmitted a message successfully

’0’: Since this bit was reset by the CPU, no message has been successfully

transmitted. This bit is never reset by the CAN Core.

’1’: Since this bit was last reset by the CPU, a message has been successfully (error

free and acknowledged by at least one other node) transmitted.

RxOk

Received a message successfully

’0’: Since this bit was last reset by the CPU, no message has been successfully

received. This bit is never reset by the CAN Core.

’1’: Since this bit was last reset (to zero) by the CPU, a message has been

successfully received (independent of the result of acceptance filtering).

EPass

Error passive

‘0’: The CAN Core is

error active.

‘1’: The CAN Core is in the

error passive state as defined in the CAN Specification.