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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AN2021 датащи(PDF) 20 Page - STMicroelectronics |
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AN2021 датащи(HTML) 20 Page - STMicroelectronics |
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20 / 39 page  Modified features AN2021 20/39 1.9.1 Hardware impact Port0 configuration might be changed with regards to the new PLL factor. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal oscillator amplifier, except for the Direct Drive mode (oscillator amplifier disabled, so no crystal or resonator can be used). Vice versa, the clock can be forced through an external clock source only in Direct Drive mode. The components on XTAL1 and XTAL2 (crystal and capacitors, or resonator) must be changed as: ● the input frequency range is now reduced ● it is no longer possible to use a crystal or a ceramic resonator in direct drive mode ● it is no longer possible to use a PLL factor with a frequency generator ● the electrical characteristics of the main oscillator have changed (transconductance) 1.9.2 Software impact None. |
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