RM0020 datasheet(58/69 Pages) STMICROELECTRONICS

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Performance

RM0020

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Performance

This section shows the code size and clock cycles for each function. The clock cycles were

measured for the following conditions:

●

Code Memory (Internal Flash) - cache on

●

Data Memory (Internal RAM) - cache on

●

Stack Memory - locked in cache

●

Data acquired on the MPC5554 with SIU_MIDR = 0x55540011

●

Branch Target Buffer (BTB) enabled

●

BIUCR = 0x00094BFD

The “Improvement to C function” column shows performance increase comparing the

assembly code to a respective C function, the value is calculated as a ratio of the

number_of_clock_cycles_of_C_ function/number_of_clock_cycles_of_optimized_ library_

function. The number of clock cycles are taken for the third function call. The C-code was

compiled in CodeWarrior for PowerPC V1.5 beta2, Global Optimizations set to level 4,

Optimize for Faster Execution Speed, Instruction Scheduling and Peephole Optimization

turned on.

The IPC column shows instructions per cycle.

Table 31.

Code size

Function

Code size [bytes]

bitrev_table_16bit

168

bitrev_table_32bit

168

fft_radix4_float

1216

fft_radix4_frac32 - scaling off

1224

fft_radix4_frac32 - scaling on

1344

fft_quad_float

1268

fft_quad_frac32 - scaling off

1276

fft_quad_frac32 - scaling on

1388

fft_radix2_last_stage_float

324

fft_radix2_last_stage_frac32 - scaling off

328

fft_radix2_last_stage_frac32 - scaling on

368

fft_real_split_float

452(1)

fft_real_split_frac32 - scaling off

452(1)

fft_real_split_frac32 - scaling on

460(2)

window_apply_complex_float

260

window_apply_complex_frac16

244(3)

window_apply_real_float

172

window_apply_real_frac16

172

mfb50_pmh

1100

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