SPC564Axx/SPC56ELxx exception cases

AN4417

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Maintaining of ECSM_ESR register to be performed properly!

For more details see Section Appendix B: Reference documents.

3.1.4

ECSM_ESR.FNCE implementation note for SPC564A70 device only

Flash controller always reads one complete prefetch buffer line (128-bit) from flash array.

ECSM_ESR.FNCE bit detects ECC error separately for double word A (bit 0..63) and

double word B (bit 64..127) in SPC564A70 device, and it can cause an unexpected

behavior.

Following is an example to demonstrate it:

Assuming that an ECC error is present in upper word and lower word is accessed by core.

Then the ECC error is detected during complete 128-bit line reading and core Machine

check exception is invoked, but ECSM_ESR.FNCE bit is not set in this case. If Machine

check exception handler tests the ECSM_ESR.FNCE bit only in our case, then it may

unexpectedly assume that no ECC issue occurred.

Note:

There is a possibility to check Flash_A.MCR.EER bit instead of the ECSM_ESR.FNCE. The

implementation depends on the application needs.

For more details see Section Appendix A: Comparison of microcontroller behavior during

ECC error.

3.1.5

ECSM_ESR implementation for SPC56ELx device only

SPC56ELx devices have been designed with functional safety in mind. In case the reporting

of dual bit errors is enabled in the ECSM, the device reacts in one of the safest way, i.e. a

critical fault is triggered by the FCCU. The outcome of this critical fault is a functional reset

of the device without any exception triggered to the core. Rational for this severe reaction is

that since the dual bit error cannot be corrected, software is not able to recover it. Then

safest reaction is assumed to be a reset.

Nevertheless this reset reaction prevents working correctly most of flash eeprom emulation

drivers. An ECC error is a standard error situation during read in flash area used for data

eeprom emulation. This situation is handled by the driver accordingly.

In case of the dual bit error, reporting is disabled in the ECMS and then a core exception is

invoked instead of reset. Core exception handler gives possibility to the flash eeprom

emulation driver to react accordingly.

3.1.6

Flash 2b ECC error detection by Flash controller

Flash controller provides detection ability of ECC errors detection.

ECSM_ESR.F1BC A reportable single-bit platform flash correction has been detected.

ECSM_ESR.FNCE A reportable non-correctable platform flash error (2b ECC) has been detected.

Table 6. Flash 2b ECC – ECSM registers related to ECC error detection (continued)

Register

Description