ECC logic test

AN4287

22/27

DocID024464

Rev 2

5.3

UTEST mode ECC logic check

The procedure to use the UTEST mode ECC logic check is listed as below:

•

Enable UTEST mode (Write 0xF9F9_9999 to UT0 register, UT0[UTE] will be set).

•

Write UT0[SBCE] to 1 (to enable single-bit error correction visibility).

•

Write UT0[EIE] to 1.

•

Write UT0[DSI], UT1[DAI] and/or UT2[DAI] bits to provide data and check bit values to

be read. Single or Double bit detections/corrections can be simulated by properly

choosing Data and Check Bit combinations.

•

Write double word address to receive the data inputted in step 3 into the ADR register.

•

Reads can now be done through the BIU in a Read Request type fashion. In the event

of a BIU read requested from an address that matches the address in the ADR register,

expected data, and corrections or detections should be observed based on data written

into the UT0[DSI], UT1[DAI] and/or UT2[DAI] registers. MCR[EER] and

MCR[SBCSBC] can be checked to evaluate the status of reads done.

•

Repeat steps 4 to 6 for all the data vectors in the proposed test data pattern.

•

Once completed, clear the UT0[EIE] bit to 0.

5.4

Fault coverage and execution time

The described ECC logic test reaches a 92.7% fault coverage of ECC decode logic.

The execution of the test code takes about 176

μs at 80 MHz, room temperature and

nominal voltages.