Data Sheet S13392EJ1V0DS00

21

10. LCD TIMING GENERATOR CIRCUIT

If master mode is entered by setting MS to H, /FRM and STB are generated at a timing that is 1/160 of the duty

ratio, and driver voltage selection signals L1 and L2 are generated for the row driver.

/FRM is generated twice per frame, STB 81 times per 1/2 frame or 162 times per frame.

(1) /FRM, STB signal generation

OSC1

PULSE

STB

/FRM

STB

81

Frame

1

2

81

1

2

81

1

2

12

(2) L1, L2 signal generation

STB

1

2

3

4

…

12

34

…

1

234

…

12

34

…

L1

11

11

…

11

11

…

0

000

…

00

00

…

L2

10

10

…

01

01

…

0

101

…

10

10

…