ACE25C160G

Uniform SECTOR Dual and Quad Serial Flash

VER 1.5

13

Write Status Register (WRSR) (01H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register.

Before it can be accepted, a Write Enable (WREN) command must previously have been executed.

After the Write Enable (WREN) command has been decoded and executed, the device sets the Write

Enable Latch (WEL).

The Write Status Register (WRSR) command has no effect on S15, S1 and S0 of the Status

Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in.

If not, the Write Status Register (WRSR) command is not executed. If CS# is driven high after eighth

bit of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. As soon as CS# is driven

high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write

Status Register cycle is in progress, the Status Register may still be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status

Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch

(WEL) is reset.

The Write Status Register (WRSR) command allows the user to change the values of the Block

Protect (SEC, TB, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as

read-only, as defined in Table1. The Write Status Register (WRSR) command also allows the user to

set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect

(WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal

allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR)

command is not executed once the Hardware Protected Mode is entered.

Figure5. Write Status Register Sequence Diagram

Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out

on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first

byte addressed can be at any location. The address is automatically incremented to the next higher

address after each byte of data is shifted out. The whole memory can, therefore, be read with a

single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase,

Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in

progress.